Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Evolution of Robustness in an Electronics Design
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Identification and authentication of integrated circuits: Research Articles
Concurrency and Computation: Practice & Experience - Computer Security
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Proceedings of the 32nd annual international symposium on Computer Architecture
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Techniques for the creation of digital watermarks in sequential circuit designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Local watermarks: methodology and application to behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Active control and digital rights management of integrated circuit IP cores
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Integrated circuits metering for piracy protection and digital rights management: an overview
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Integrated circuit digital rights management techniques using physical level characterization
Proceedings of the 11th annual ACM workshop on Digital rights management
Robust passive hardware metering
Proceedings of the International Conference on Computer-Aided Design
Scalable segmentation-based malicious circuitry detection and diagnosis
Proceedings of the International Conference on Computer-Aided Design
Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
A zero-overhead IC identification technique using clock sweeping and path delay analysis
Proceedings of the great lakes symposium on VLSI
Can EDA combat the rise of electronic counterfeiting?
Proceedings of the 49th Annual Design Automation Conference
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Capturing post-silicon variation by layout-aware path-delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware security: threat models and metrics
Proceedings of the International Conference on Computer-Aided Design
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We have developed a methodology for unique identification of integrated circuits (ICs) that addresses untrusted fabrication and other security problems. The new method leverages nondestructive gate-level characterization of ICs post-manufacturing, revealing the hidden and unclonable uniqueness of each IC. The IC characterization uses the externally measured leakage currents for multiple input vectors. We have derived several optimization techniques for gate-level characterization. The probability of collision of IDs in presence of intra- and inter-chip correlations is computed. We also introduce a number of novel security and authentication protocols, such as hardware metering , challenge-based authentication and prevention of software piracy , that leverage the extraction of a unique ID for each IC. Experimental evaluations of the proposed approach on a large set of benchmark examples reveals its effectiveness even in presence of measurement errors.