Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
N-variant IC design: methodology and applications
Proceedings of the 45th annual Design Automation Conference
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Recently, the electronic design automation industry has adopted the intellectual property (IP) business model as a dominant system-on-chip development platform. Since copyright fraud has been recognized as the most devastating obstruction to this model, a number of techniques for IP protection have been introduced. Most of them rely on a selection of a global solution to a design optimization problem according to a unique user-specific digital signature. Although such techniques provide strong proof of authorship, they fail to provide an effective procedure for watermark detection when a protected core design is augmented into a larger design. To address this fundamental issue, we introduce local watermarks, an IP protection technique which facilitates watermark detection in many realistic design and adversarial scenarios, while satisfying the demand for low overhead and design transparency. We demonstrate the efficiency of the new IP protection paradigm by applying its principles to a set of behavioral synthesis tasks such as operation scheduling and template matching.