On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-Silicon Timing Validation Method Using Path Delay Measurements
ATS '11 Proceedings of the 2011 Asian Test Symposium
Active learning framework for post-silicon variation extraction and test cost reduction
Proceedings of the International Conference on Computer-Aided Design
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With aggressive device scaling, the impact of parameter variation is becoming more prominent, which results in the uncertainty of a chip's performance. Techniques that capture post-silicon variation by deploying on-chip monitors suffer from serious area overhead and low testing reliability, while techniques using non-invasion test are limited in small scale circuits. In this paper, a novel layout-aware post-silicon variation extraction method which is based on non-invasive path-delay test is proposed. The key technique of the proposed method is a novel layout-aware heuristic path selection algorithm which takes the spatial correlation and linear dependence between paths into consideration. Experimental results show that the proposed technique can obtain an accurate timing variation distribution with zero area overhead. Moreover, the test cost is much smaller than the existing non-invasion method.