Capturing post-silicon variation by layout-aware path-delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
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In the nanometer era, the mismatch between the pre-silicon model and the post-silicon timing behavior is becoming severer. Therefore, it is necessary to validate timing with post-silicon data. We propose a method that estimates all the segment delays in the observed paths of a design from post-silicon path delay measurements. Our method is based on equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. Experimental results show that segment delays obtained using our method achieved correlation ranged from 0.848 to 0.992 to the sampled segment delays for different ISCAS-85 benchmark circuits.