SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode. The signature of the owner of physical design tool along with that of logic design tool can separately be embedded while designing the scan tree and also verified from the packaged chip without conflict using two distinct modes. A bi-objective minimization of overhead in routing and power is supported through our scheme. Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.