Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers as components: principles of embedded computing system design
Computers as components: principles of embedded computing system design
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Smart Cameras as Embedded Systems
Computer
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Guaranteeing the quality of services in networks on chip
Networks on chip
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Exact and efficient crosstalk estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Slicing floorplan with clustering constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
UNION: a unified inter/intra-chip optical network for chip multiprocessors
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networks-on-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.