A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Performance Evaluation of the ServerNet R SAN under Self-Similar Traffic
IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
An Analytical Performance Model for the Spidergon NoC
AINA '07 Proceedings of the 21st International Conference on Advanced Networking and Applications
The m-pancycle-connectivity of a WK-Recursive network
Information Sciences: an International Journal
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
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Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.