Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network

Authors:
S. Suboh;M. Bakhouya;T. El-Ghazawi
Affiliations:
-;-;-
Venue:
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Year:
2008

Citing 3
Cited 1

A recursively scalable network VLSI implementation

Future Generation Computer Systems
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Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh

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Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

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Abstract

Network-on-chip has been proposed as an alternative to bus-based system to achieve high performance and scalability. The topology of on-chip interconnect plays a crucial role in System on chip performance, energy, and area requirements. In this paper, an on-chip interconnects architecture based on WK-recursive network is proposed. WK-recursive structure is analyzed and compared to 2D mesh and Spidergon structures. Simulation results show that WK-Recursive on-chip interconnect generally outperforms the other architectures.