Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fpga-based prototype of a pram-on-chip processor
Proceedings of the 5th conference on Computing frontiers
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Proceedings of the 45th annual Design Automation Conference
Application-specific Processor Architecture: Then and Now
Journal of Signal Processing Systems
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
Lazy binary-splitting: a run-time adaptive work-stealing scheduler
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
OTIS-MOT: an efficient interconnection network for parallel processing
The Journal of Supercomputing
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison
International Journal of High Performance Systems Architecture
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
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For some time now, configurable computing has been hailed as the future for application-specific architectures. The purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, ...