The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic
ARTCOM '09 Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
International Journal of High Performance Systems Architecture
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This paper presents a new dimension ordered routing (DOR) algorithm for mesh-of-tree (MoT)-based network-on-chip (NoC) designs. A simple addressing scheme has been used in this new algorithm. The addressing scheme enables us to reduce the minimum flit-size for a 4 × 4 MoT to 16 bits, compared to 32 bits in the previously reported works. The algorithm has been proved to be deadlock, live-lock and starvation free. It also ensures shortest-path routing for the packets. It results in significant saving in the energy consumed by the network. It allows us to vary router complexity flexibly while planning the MoT-based NoC for application specific system-on-chip (SoC) synthesis. Performance and cost metric comparison with other topologies shows the proposed MoT to be better than many of them.