Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison
International Journal of High Performance Systems Architecture
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
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Network-on-Chip (NoC) is a new paradigm for designing future SoCs. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present Mesh-of-Tree (MoT) based deterministic routing for NoC architecture. MoT interconnection has the advantage of having small diameter as well as large bisection width. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock and livelock free.