Design and implementation of a reconfigurable arbiter

Authors:
Yu-Jung Huang;Yu-Hung Chen;Chien-Kai Yang;Shih-Jhe Lin
Affiliations:
Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, ROC;Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, ROC;Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, ROC;Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, ROC
Venue:
SSIP'07 Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing
Year:
2007

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Abstract

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP). Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 µm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. The reconfigurable arbiter can be custom-tuned to obtain high bandwidth utilization, low latency, and power effective for on-chip bus communication.