Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
IEEE Transactions on Computers
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A task graph execution manager for reconfigurable multi-tasking systems
Microprocessors & Microsystems
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Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performance. One reason is that tasks can run in parallel but configurations of the tasks can be done only in sequence. This work presents a novel configuration model to enable configuration parallelism. It consists of multiple homogeneous tiles and each tile has its own configuration SRAM that can be individually accessed. Thus multiple configuration controllers can load tasks in parallel and more speedups can be achieved. We used a prefetch scheduling technique to evaluate the model with randomly generated tasks. The experiment results reveal that in average using multiple controllers can reduce the configuration overheads by 21%. Compared to best cases of using multiple tiles with a single controller, additional 40% speedup can be achieved using multiple controllers.