Dynamic Reconfiguration to Support Concurrent Applications
IEEE Transactions on Computers
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Higher-Dimensional Packing with Order Constraints
WADS '01 Proceedings of the 7th International Workshop on Algorithms and Data Structures
Proceedings of the 41st annual Design Automation Conference
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
A Combinatorial Characterization of Higher-Dimensional Orthogonal Packing
Mathematics of Operations Research
Proceedings of the 42nd annual Design Automation Conference
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Improving utilization of reconfigurable resources using two-dimensional compaction
The Journal of Supercomputing
Intelligent merging online task placement algorithm for partial reconfigurable systems
Proceedings of the conference on Design, automation and test in Europe
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware task scheduling and placement in operating systems for dynamically reconfigurable soc
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Partially reconfigurable field programmable gate arrays (FPGAs) can accommodate several independent tasks simultaneously. FPGA, as all reconfigurable chips, relies on the "host-then-compact-when-needed" strategy. Accordingly, it should have the ability to both place incoming tasks at run time and compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations problem, trying to move running tasks closer to each other in order to free a sufficient area for new tasks. However, compaction conditions the suspension of the running tasks, which introduces a high penalty. In order to increase the chip area utilization as well as not affecting the response times of tasks, efficient compaction techniques become increasingly important. Unfortunately, traditional compaction techniques suffer from a variety of faults. This paper introduces a novel Puzzle Based Compaction (PBC) technique that is a shape aware technique, which takes the tasks shapes into consideration. In this regard, it succeeded not only to eliminate the internal fragmentations but also to minimize the external fragmentations. This paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by accommodating a set of tasks inside the reconfigurable chip.