Sequencing run-time reconfigured hardware with software
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs
IEEE Transactions on Computers
Deterministic Processor Scheduling
ACM Computing Surveys (CSUR)
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Scaling genetically guided fuzzy clustering
ISUMA '95 Proceedings of the 3rd International Symposium on Uncertainty Modelling and Analysis
Automatic Target Recognition with Dynamic Reconfiguration
Journal of VLSI Signal Processing Systems
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Distributed arithmetic FPGA design with online scalable size and performance
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Improving utilization of reconfigurable resources using two-dimensional compaction
The Journal of Supercomputing
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
Proposal for an efficient reconfigurable fixed-width multiplier
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Performance optimization of error detection based on speculative reconfiguration
Proceedings of the 48th Design Automation Conference
International Journal of Applied Evolutionary Computation
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This paper describes the development of a dynamically reconfigurable system that can support multiple applications running concurrently. A dynamically reconfigurable system allows hardware reconfiguration while part of the reconfigurable hardware is busy computing. An FPGA resource manager (RM) is developed to allocate and de-allocate FPGA resources and to preload FPGA configuration files. For each individual application, different tasks that require FPGA resources are represented as a flow graph which is made available to the RM so as to enable efficient resource management and preloading. The performance of using the RM to support several applications is summarized. The impact of supporting concurrency and preloading in reducing application execution time is demonstrated.