Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Dynamic Reconfiguration to Support Concurrent Applications
IEEE Transactions on Computers
Multitasking on FPGA Coprocessors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Preemptive Multitasking on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Use of preferred preemption points in cache-based real-time systems
IPDS '95 Proceedings of the International Computer Performance and Dependability Symposium on Computer Performance and Dependability Symposium
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Micropreemption synthesis: an enabling mechanism for multitask VLSI systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Task preemption is a critical mechanism for building an effective multitasking environment on dynamically reconfigurable processors. When being preempted, necessary state information of the interrupted task in registers and distributed internal memories must be correctly preserved. This paper aims at studying a method for saving and restoring the state data of a hardware task, executing on a dynamically reconfigurable processing array, taking into account the great amount and the distribution on different storage elements of data. Performance degradation caused by task preemption is minimized by allowing preemption only at predefined points where demanded resources are small. Specifically, we propose: 1) algorithms to insert preemption points subject to user-specified preemption latency and resource overhead constraints; 2) modification steps to incorporate the offered algorithms on the system design flow. Evaluation results on the NEC DRP architecture show that the proposed method achieves a reasonable hardware overhead (from 6% to 14%) while satisfying a given preemption latency.