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CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Scheduling of conditional process graphs for the synthesis of embedded systems
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference
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Proceedings of the 38th annual Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
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Proceedings of the conference on Design, automation and test in Europe
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Energy efficient multiprocessor task scheduling under input-dependent variation
Proceedings of the Conference on Design, Automation and Test in Europe
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Task scheduling for look–ahead reconfigurable systems in presence of conditional branches
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
Mapping on multi/many-core systems: survey of current and emerging trends
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UCC '13 Proceedings of the 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing
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This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.