Scheduling precedence graphs in systems with interprocessor communication times
SIAM Journal on Computing
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISPDC '04 Proceedings of the Third International Symposium on Parallel and Distributed Computing/Third International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks
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A new program structuring algorithm for dynamically look–ahead reconfigurable multi–processor systems is presented in the paper. The presented algorithm uses a new kind of graph representation of parallel programs with conditional branches (Branching Task Graph, BTG). The BTG captures the data–flow and control–flow properties of parallel programs. It extends the scope of parallel programs optimized for execution in look–ahead reconfigurable systems beyond static DAG graphs. The new program graph structuring algorithm for BTG graphs is based on a two–phase approach. It consists of a new list task scheduling heuristics, which incorporates branch optimization techniques such as detection of mutually–exclusive subgraphs and scheduling of most–often–used paths based on branch probabilities. In the second phase, program partitioning into sections executed with the look–ahead created connections is done, based on the modified iterative clustering heuristics.