A case for FAME: FPGA architecture model execution
Proceedings of the 37th annual international symposium on Computer architecture
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput
Proceedings of the 38th annual international symposium on Computer architecture
Exploring irregular memory accesses on FPGAs
Proceedings of the first workshop on Irregular applications: architectures and algorithm
A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
The dynamic granularity memory system
Proceedings of the 39th Annual International Symposium on Computer Architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
International Journal of High Performance Computing Applications
A locality-aware memory hierarchy for energy-efficient GPU architectures
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Compiled multithreaded data paths on FPGAs for dynamic workloads
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instruction sets. Managing the decoding, dispatch, and execution of completely user-defined instructions requires an innovative approach to system design and operation.