Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
High-level software energy macro-modeling
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
Parallel simulation of chip-multiprocessor architectures
ACM Transactions on Modeling and Computer Simulation (TOMACS)
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Rapid Resource-Constrained Hardware Performance Estimation
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A Platform-Based Taxonomy for ESL Design
IEEE Design & Test
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Is a Unified Methodology for System-Level Design Possible?
IEEE Design & Test
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
ESL power analysis of embedded processors for temperature and reliability estimations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
A comparison of active queue management algorithms using the OPNET Modeler
IEEE Communications Magazine
RTL-Aware Cycle-Accurate Functional Power Estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Software energy optimization through fine-grained function-level voltage and frequency scaling
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
From RTL IP to functional system-level models with extra-functional properties
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Run-time resource management based on design space exploration
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Network-aware design-space exploration of a power-efficient embedded application
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SystemC Model Generation for Realistic Simulation of Networked Embedded Systems
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The consideration of an embedded device's power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.