Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Proceedings of the 46th Annual Design Automation Conference
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
IEEE Transactions on Computers
Microprocessors & Microsystems
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The paper presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10\% of the abstracted model's power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.