A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

Authors:
L. Bissi;P. Placidi;G. Baruffa;A. Scorzoni
Affiliations:
Dipartimento di Ingegneria Elettronica e dell'Informazione (DIEI), Universití degli Studi di Perugia, via G. Duranti 93, I-06125 Perugia, Italy;Dipartimento di Ingegneria Elettronica e dell'Informazione (DIEI), Universití degli Studi di Perugia, via G. Duranti 93, I-06125 Perugia, Italy;Dipartimento di Ingegneria Elettronica e dell'Informazione (DIEI), Universití degli Studi di Perugia, via G. Duranti 93, I-06125 Perugia, Italy;Dipartimento di Ingegneria Elettronica e dell'Informazione (DIEI), Universití degli Studi di Perugia, via G. Duranti 93, I-06125 Perugia, Italy
Venue:
Integration, the VLSI Journal
Year:
2008

Citing 3
Cited 1

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Dynamic partial reconfigurable Viterbi decoder for wireless standards

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Abstract

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2Mbps, with an area occupancy of 46%, due to the efficient resources reuse.