Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS

Authors:
Matthias Kamuf;Joachim Neves Rodrigues;John B. Anderson;Viktor Öwall
Affiliations:
Dept. of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden and Ericsson AB, Scheelevägen 19 C, 223 63 Lund, Sweden;Dept. of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden;Dept. of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden;Dept. of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden
Venue:
Microprocessors & Microsystems
Year:
2010

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Abstract

This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.