Power characterisation for fine-grain reconfigurable fabrics

Authors:
Tobias Becker;Peter Jamieson;Wayne Luk;Peter Y. K. Cheung;Tero Rissa
Affiliations:
Department of Computing, Imperial College London, London, UK;Department of Computing, Imperial College London, London, UK;Department of Computing, Imperial College London, London, UK;Department of EEE, Imperial College London, London, UK;Nokia Devices R&D, Tampere, Finland
Venue:
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Year:
2010

Citing 11
Cited 1

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Abstract

This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.