Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Power characterisation for fine-grain reconfigurable fabrics
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Feasibility analysis of reconfigurable computing in low-power wireless sensor applications
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Proceedings of the International Conference on Computer-Aided Design
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
Optimizing effective interconnect capacitance for FPGA power reduction
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns