A methodology for FPGA to structured-ASIC synthesis and verification

Authors:
Mike Hutton;Richard Yuan;Jay Schleicher;Gregg Baeckler;Sammy Cheung;Kar Keng Chua;Hee Kong Phoo
Affiliations:
Altera Corp., San Jose, CA;Altera Corp., San Jose, CA;Altera Corp., San Jose, CA;Altera Corp., San Jose, CA;Altera Corp., San Jose, CA;Altera Corp., Penang, Malaysia;Altera Corp., Penang, Malaysia
Venue:
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Year:
2006

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Abstract

Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. The most important aspects of this methodology are the use of physically identical blocks for difficult-to-verify PLLs, I/O and RAM and a structured re-synthesis of FPGA logic blocks to target cells that guarantees anchor points for easy formal verification.