Division Algorithms and Implementations
IEEE Transactions on Computers
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root
IEEE Transactions on Computers
A New Divide and Conquer Method for Achieving High Speed Division in Hardware
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
The IBM eServer z990 floating-point unit
IBM Journal of Research and Development
High Speed Redundant Adder and Divider in Output Prediction Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An improved division algorithm with a small lookup table and its implementation
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Increasing throughput of a RISC architecture using arithmetic data value speculation
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a high precision logarithmic converter in a binary floating point divider
Concurrency and Computation: Practice & Experience
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SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider architectures and circuit families on divider area and performance. We show the performance and area results for a wide variety of divider architectures and implementations. We conclude that divider performance is only weakly sensitive to reasonable choices of architecture but significantly improved by aggressive circuit techniques.