Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Division Algorithms and Implementations
IEEE Transactions on Computers
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FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
SRT Division Architectures and Implementations
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
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RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
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This paper presents an improved Hung's division algorithm, which can produce results with very low latency. In our method, a computing error bound is given, and a set of the optimum design parameters is provided. According to our design approach, hardware scale is significantly reduced, comparing with the original method. Our algorithm has been implemented on Xilinx FPGA, as kernel of channel estimator in an OFDM receiver. The results of hardware simulation show that the divider error, which is well controlled by our error bounds, satisfies our design requirements.