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This paper presents an implementation of a channelequalizer for a wireless OFDM according to the IEEE802.11a and Hiperlan/2 standard. In order to implementthe equalizer, algorithms of low computational complexityhave been analyzed. A rapid prototype design flow ispresented and applied to the prototyping of these equalizeralgorithms in real time on a FPGA platform. A new point ofview in the prototyping design flow and the verificationprocess is achieved through the last generation system leveldesign environments for DSPs into FPGAs. Theseenvironments, called visual data flows, are ideally suitedfor modeling DSP systems, since they allow a high level offunctional abstraction with different data types andoperators. The implemented channel equalizer reaches ahigh degree of hardware simplicity and efficiency, coveringthe standard specifications.