Increasing throughput of a RISC architecture using arithmetic data value speculation

Authors:
Daniel R. Kelly;Braden J. Phillips;Said Al-Sarawi
Affiliations:
Centre for High Performance Integrated Technologies and Systems, University of Adelaide, Australia;Centre for High Performance Integrated Technologies and Systems, University of Adelaide, Australia;Centre for High Performance Integrated Technologies and Systems, University of Adelaide, Australia
Venue:
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Year:
2009

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Abstract

Arithmetic data value speculation (ADVS) is a scheme to increase the throughput of a processor pipeline similar to conventional branch prediction. An approximate arithmetic unit, with an associated probability of correctness, provides an approximate result earlier than an exact unit, allowing the speculative issue of dependent operations. This paper investigates the performance gain in terms of retired instructions per clock (IPC) by employing ADVS in a RISC processor. Simulated results show the effect of probability of correctness and latency of approximate arithmetic units on IPC. In particular, minimum requirements for approximate arithmetic units are characterized, and maximum increase in IPC is shown for typical benchmark applications.