Compiler-in-the-loop design space exploration framework for energy reduction in horizontally partitioned cache architectures

Authors:
Aviral Shrivastava;Ilya Issenin;Nikil Dutt;Sanghyun Park;Yunheung Paek
Affiliations:
Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Center for Embedded Computer System, School of Information and Computer Science, University of California at Irvine, Irvine, CA;Center for Embedded Computer System, School of Information and Computer Science, University of California at Irvine, Irvine, CA;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 6
Cited 1

A data cache with multiple caching strategies tuned to different types of locality

ICS '95 Proceedings of the 9th international conference on Supercomputing
The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability

DATE '99 Proceedings of the conference on Design, automation and test in Europe
XTREM: a power simulator for the Intel XScale® core

Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Compilation techniques for energy reduction in horizontally partitioned cache architectures

Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

Horizontally partitioned caches (HPCs) are a power-efficient architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. HPCs help reduce cache pollution and thereby improve performance. Consequently, most previous research has focused on exploiting HPCs to improve performance and achieve energy reduction only as a byproduct of performance improvement. However, with energy consumption becoming the first class design constraint, there is an increasing need for compilation techniques aimed at energy reduction itself. This paper proposes and explores several low-complexity algorithms aimed at reducing the energy consumption. Acknowledging that the compiler has a significant impact on the energy consumption of the HPCs, Compiler-in-the-Loop Design Space Exploration methodologies are also presented to carefully choose the HPC parameters that result in minimum energy consumption for the application.