Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On lower bounds for scheduling problems in high-level synthesis
Proceedings of the 37th Annual Design Automation Conference
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
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The authors present a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the scheduling problem. This tight, yet fairly efficient, bounding method can be used to estimate FU area, to generate resource constraints for reducing the search space, or in conjunction with exact techniques for efficient optimal design space exploration.