Efficient hardware controller synthesis for synchronous dataflow graph in system level design

Authors:
Hyunuk Jung;Kangnyoung Lee;Soonhoi Ha
Affiliations:
School of Electrical Engineering and Computer Science, Seoul National University, Seoul, 151-744, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, 151-744, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, 151-744, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous works with some examples, the novelty of the proposed technique is demonstrated.