Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multidimensional DSP Core Synthesis for FPGA
Journal of VLSI Signal Processing Systems
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows
Journal of VLSI Signal Processing Systems
Simplifying physical realization of Gaussian particle filters with block-level pipeline control
EURASIP Journal on Applied Signal Processing
A systematic approach to design low-power video codec cores
EURASIP Journal on Embedded Systems
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
A generalized scheduling approach for dynamic dataflow applications
Proceedings of the Conference on Design, Automation and Test in Europe
Heterogeneous design in functional DIF
Transactions on High-Performance Embedded Architectures and Compilers IV
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