Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code Generation of Data Dominated DSP Applications for FPGA Targets
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
A design methodology for low-power heterogeneous reconfigurable digital signal processors
A design methodology for low-power heterogeneous reconfigurable digital signal processors
Simplifying physical realization of Gaussian particle filters with block-level pipeline control
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a flexible controller structure for concurrent processing of memory centric coarse grain data flows. We propose a design flow based on block level pipelining where concurrency among processing blocks is fully maintained. The controller is dynamically reconfigurable to support dynamic data-flow structure changes by localizing control signals. The proposed control design method isolates controllers and processing logics such that system integration is simplified while controllers are locally configured from orthogonal global information. The controller also supports interfacing with external processors for asynchronous processing. The controller for heterogeneous processing blocks is synthesized and verified using Verilog and SystemC on FPGA. We present an example demonstrating the effectiveness of the controllers where dynamic reconfiguration of the execution is feasible.