Optimal synthesis of multichip architectures
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-power architectural synthesis and the impact of exploiting locality
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling with multiple voltages
Integration, the VLSI Journal
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Synthesis of VLSI systems with the CAMAD design aid
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
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This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and the timing or the resource constraints. In the paper, partitioning is considered with scheduling in the proposed algorithms as multiple voltage design can lead to an increase in interconnection complexity at layout level. That is, in the proposed algorithms power consumption is first reduced by the scheduling step, and then the partitioning step takes over to decrease the interconnection complexity. Both time-constrained and resource-constrained algorithms have time complexity of o(n2), where n is the number of nodes in the DFG. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve the power reduction under timing constraints and resource constraints by an average of 46.5 and 20%, respectively.