Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Energy minimization using multiple supply voltages
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power optimization of variable voltage core-based systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
On-line scheduling of hard real-time tasks on variable voltage processor
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
What is the limit of energy saving by dynamic voltage scaling?
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimal voltage allocation techniques for dynamically variable voltage processors
Proceedings of the 40th annual Design Automation Conference
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Multivoltage scheduling with voltage-partitioned variable storage
Proceedings of the 2003 international symposium on Low power electronics and design
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal voltage allocation techniques for dynamically variable voltage processors
ACM Transactions on Embedded Computing Systems (TECS)
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
Multiple voltage synthesis scheme for low power design under timing and resource constraints
Integrated Computer-Aided Engineering
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Power optimization for simultaneous scheduling and partitioning with multiple voltages
MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering
WSEAS Transactions on Signal Processing
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
Temperature aware datapath scheduling
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an algorithm called MOVER (Multiple Operating Voltage Energy Reduction) to minimize datapath energy dissipation through use of multiple supply voltages. In a single voltage design, the critical path length, clock period, and number of control steps limit minimization of voltage and power. Multiple supply voltages permit localized voltage reductions to take up remaining schedule slack. MOVER initially finds one minimum voltage for an entire datapath. It then determines a second voltage for operations where there is still schedule slack. New voltages con be introduced and minimized until no schedule slack remains. MOVER was exercised for a variety of DSP datapath examples. Energy savings ranged from 0% to 50% when comparing dual to single voltage results. The benefit of going from two to three voltages never exceeded 15%. Power supply costs are not reflected in these savings, but a simple analysis shows that energy savings can be achieved even with relatively inefficient DC-DC converters. Datapath resource requirements were found to vary greatly with respect to number of supplies. Area penalties ranged from 0% to 170%. Implications of multiple voltage design for IC layout and power supply requirements are discussed.