Multiple voltage synthesis scheme for low power design under timing and resource constraints

  • Authors:

  • Ling Wang;Yingtao Jiang;Henry Selvaraj

  • Affiliations:

  • Department of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001, China;Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV 89154, USA;Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV 89154, USA

  • Venue:
  • Integrated Computer-Aided Engineering
  • Year:
  • 2005

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Abstract

In this paper, a tabu-search-based behavior level synthesis scheme is proposed to minimize chip power consumption with resources operating at multiple voltages under the timing and resource constraints. Unlike the conventional methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. More importantly, our approach tends to efficiently address a few practical layout problems inherent to multiple voltage designs. In particular, we have configured our solutions as a three-tuple vector to account for both the schedule and the partition. Cycling of the same solutions is prevented by applying a tabu list with an update mechanism enhanced with an aspiration function. In this way, the algorithm can search a large solution space with modest computation effort and fast convergence rate. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve an average power reduction by 49.6%