Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Path concepts for a reconfigurable bit-serial synchronous architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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In this paper, we present an approach for low--power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High--Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input- and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).