Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
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This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and systematic bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture. The example – implementing both algorithms in one operator network – broadens the application area of the architecture significantly.