Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Path concepts for a reconfigurable bit-serial synchronous architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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This paper presents high-level synthesis methods for a fully reconfigurable self-timed synchronous bit-serial pipeline architecture. The idea is to distribute the central control unit. Local controls of the operators are realized through a one-hot implementation of the central control engine. Specialized routing components allow the reconfiguration of the implemented circuit with respect to rapid system prototyping. We describe several kinds of high-level synthesis approaches, especially the scheduling, which can be used for this type of architecture. This means we optimize specific characteristics, like loops, junctions and splitters, during the synthesis phase.