Circuits,signals,and systems
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Embedded System Design
Path concepts for a reconfigurable bit-serial synchronous architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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This paper presents latency optimizations for a specific hard-ware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing with-out a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.