Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
Path concepts for a reconfigurable bit-serial synchronous architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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The growing need for application class specific but still flexibledata processing leads to a demand of new computer architectures.Reorganziation and combination of proven designparadigms are promising ways to reach these goals.The fully reconfigurable self-timed bit-serial and fully interlockedMACT architecture is one of those new architectures.Although MACT does not rely on a central controller, its localsynchronization still demands special care is taken. Thisfact is especially true if routers are added to the architecture.In this paper we present fundamental invariants for the highlevel synthesis of MACT as well as an extended explanationof the routing elements. We prove the usefulness of the architectureby an example implementation of two convolutionfilters within one data flow graph.