VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper describes the implementation of the Advanced Encryption Standard (AES) for a specific hardware architecture, which was developed based on the combination of different design paradigms. The architecture comprises synchronous and systematic bit---serial processing without a central controlling instance. To realize the AES cipher, we extended the architecture by designing specific elements. That means, we deeply analyzed the encryption algorithm and identified hardware characteristics leading to an optimal area and run---time efficient implementation. The implementation of AES is done with the developed synthesis tool of the hardware architecture in synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran some tests on an FPGA board.