Power optimization for simultaneous scheduling and partitioning with multiple voltages

Authors:
Dongxin Wen;Ling Wang;Yingtao Jiang;Henry Selvaraj
Affiliations:
Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, Heilongjiang, China;Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, Heilongjiang, China;Department of Electrical & Computer Engineering, University of Nevada, Las Vegas;Department of Electrical & Computer Engineering, University of Nevada, Las Vegas
Venue:
MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering
Year:
2005

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Abstract

This paper presents a synthesis scheme based on simulated annealing, to minimize power consumption with resources operating at multiple voltages under timing and resource constraints. The scheme considers both scheduling and partitioning simultaneously to reduce power consumption with considering layout issues. Experimental results with a number of DSP benchmarks show that the scheme can achieve significant power reduction at the expense of running time.