Stochastic evolution: a fast effective heuristic for some generic layout problems
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
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Abstract We present a graph based approach to the time (performance) constrained synthesis of multi-chip module (MCM) architectures. System-level partitioning is performed using the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. The partitioning cost function models the scheduling allocation constraints (including interchip buses) in the form of incompatible sets. Supernoades are created using the scheduling allocation constraints which in turn reduces the search space for the partitioner. Scheduling and resource allocation is performed for the case of time (performance) constrained synthesis and includes modeling of inter-chip buses, multi-cycle operations, pipelined functional units and functional pipelining. Efficient synthesis results are obtained for the high-level synthesis benchmarks in far less CPU time compared to the integer linear programming based model in [7].