MULTIPAR: behavioral partition for synthesizing multiprocessor architectures

Authors:
Yunn-Yen Chen;Yu-Chin Hsu;Chung-Ta King
Affiliations:
Department of Computer Science, Tsing-Hua University, Hsin-Chu, Taiwan;Department of Computer Science, Tsing-Hua University, Hsin-Chu, Taiwan;Department of Computer Science, University of California, Riverside, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 8
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Abstract

In this paper, we present methods for scheduling and partitioning behavioral descriptions (e.g., CDFG's) in order to synthesize application-specific multiprocessor systems. Our target application domain is digital signal processing (DSP). In order to meet the user given constraints (such as timing), maximizing the system throughput and minimizing the amount of communication between processors are important. A model of a target processor and the communication device (i.e., bus, FIFO and delay element) is defined as a basis for the synthesis. We use an integer linear programming formulating to solve the partitioning and scheduling problems simultaneously. The optimization complexity for large applications can be reduced by using a simplied formulation. For even larger applications, we propose an iterative partitioning heuristic to solve. Finally, the formulations are extended to take into account of conditional branches, loops, and critical signals.