Architectural partitioning for system level design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
A tool for partitioning and pipelined scheduling of hardware-software systems
Proceedings of the 11th international symposium on System synthesis
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Hardware resource allocation for hardware/software partitioning in the LYCOS system
Proceedings of the conference on Design, automation and test in Europe
Co-synthesis with custom ASICs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
On the hardware-software partitioning problem: System modeling and partitioning techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Proceedings of the 42nd annual Design Automation Conference
PeaCE: A hardware-software codesign environment for multimedia embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design space exploration for three-dimensional (3D) SoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Electronic System Level (ESL) design methodology has been widely adopted in SoC designing, especially for designs with multiple cores. High level synthesis is now becoming a standard tool in the ESL design flow. People use the term ESL Synthesis to suggest the solution for multicore system synthesis. In this paper we argue that ESL Synthesis is architecture synthesis, high level synthesis and software synthesis combined. A multicore architecture synthesis algorithm had been implemented and proven in an experimental industry use. We successfully synthesized the target application, a GSM Edge algorithm for base station, into single and multicore systems. With this experience we developed the theory how high level synthesis and software synthesis should work with architecture synthesis to perform the task of ESL synthesis. Possible future research directions inspired by this work are also proposed. Key contributions of this work are (1) a user-defined cost function mechanism, (2) a warranted convergence mechanism and (3) combine above two mechanisms to waive the need for a universal cost function.