Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Application of ESL synthesis on GSM edge algorithm for base station
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of complex image processing systems in ESL
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield.