High-level synthesis with pin constraints for multiple-chip designs

Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

PARAS: system-level concurrent partitioning and scheduling

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Target architecture oriented high-level synthesis for multi-FPGA based emulation

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Design-Space Exploration for Block-Processing Based TemporalPartitioning of Run-Time Reconfigurable Systems

Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology